There has been a dramatic increase in the functionality and performance of integrated circuits (IC) over the past forty years, largely due to scaling, where component sizes within ICs have been reduced (scaled) with each successive technology generation. With scaling, transistor performance and density typically improve but the wires (interconnects) that connect together the transistors degrade performance. Wires often dominate performance, functionality, and power consumption of ICs.
Sequential 3D (three-dimensional) integration of semiconductor chips (dice) is one avenue in tackling wire performance. By arranging transistors in three dimensions instead of two, one can place IC transistors closer to each other. This reduces wire length and reduces signal delay. However, there are many barriers to the practical implementation of 3D integrated chips. One such barrier is that transistor construction in ICs typically requires high temperatures (higher than about 700° C.), while wiring levels are constructed at low temperatures (lower than about 450° C.). Copper or Aluminum wiring levels may be damaged when exposed to temperatures higher than about 500° C. As such, 3D integrated IC fabrication poses several challenges.